Nanya NT6TL128M32BQ-G0 PDDR2 4Gb SDP SDRAM commercial stock

Basis LPDDR2 Compliant
– Low Power Consumption
– Double-data rate on DQs, DQS, DM and CA bus
– 4n Prefetch Architecture

Signal Integrity
– Configurable DS for system compatibility
– ZQ calibration for the accuracy of output driver
strength over Process, Voltage and Temperature

Training for Signals’ Synchronization
– DQ Calibration offering specific DQ output patterns
Data Integrity
– DRAM built-in Temperature Sensor for
Temperature Compensated Self Refresh (TCSR)
– Auto Refresh and Self Refresh Modes

Power Saving Modes
– Deep Power Down Mode (DPD)
– Partial Array Self Refresh (PASR)
– Clock Stop capability during idle period

HSUL12 interface and Power Supply
– VDD1= 1.70 to 1.95V
– VDD2/VDDQ/VDDCA = 1.14 to 1.3V

Options
Speed Grade (DataRate/Read Latency)
– 1066 Mbps / RL=8
– 800 Mbps / RL=6

Temperature Range (Tc)
– Commercial Grade = – 25 to + 85
– Industrial Grade = – 40 to + 85
– Industrial Grade Extended Temperature= – 40 to + 105 2

Programmable functions

Output Drive Impedance (34.3/40/48/60/80/120)
Burst Lengths (4/8/16)
Burst Type (Sequential/Interleaved）
Read Latency (3/4/5/6/7/8),Write Latency (1/2/3/4)
nWR (3/4/5/6/7/8)
PASR (bank/segment)

LPDDR2-S4 uses the double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information.Each command uses one clock cycle, during which command information is transferred on both the positiveand negative edge of the clock.

To achieve high-speed operation, our LPDDR2-S4 SDRAM uses the double data rate architecture and adopt 4n-prefetch interface designed to transfer two data per clock cycle at the I/O pins. A single read or write access for the LPDDR2-S4 effectively consists of a single 4n-bit wide, one clock cycle data transfer at the internal SDRAM core and four corresponding n-bit wide, one-half-clock-cycle data transfer at the I/O pins. Read and write accesses to the LPDDR2-S4 are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

For LPDDR2-S4 devices, accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Active command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst acces

Density: 4Gb
Organization: 128M x 32
Part Number: NT6TL128M32BQ-G0
Package: 168-Ball
Speed TCK (ns): 1.875
Speed Data Rate (Mb/s/pin): 1066
RL: 8