In stock NT5CC128M16JR-EK DRAM Chip DDR3L SDRAM 2Gbit 128Mx16 1.35V 96-Pin TFBGA

JEDEC DDR3 Compliant
– 8n Prefetch Architecture
– Differential Clock(CK/CK) and Data Strobe(DQS/DQS)
– Double-data rate on DQs, DQS and DM

Data Integrity
– Auto Self Refresh (ASR) by DRAM built-in TS
– Auto Refresh and Self Refresh Modes

Power Saving Mode
– Power Down Mode

Signal Integrity
– Configurable DS for system compatibility
– Configurable On-Die Termination
– ZQ Calibration for DS/ODT impedance accuracy via
external ZQ pad (240 ohm ± 1%)

Signal Synchronization
– Write Leveling via MR settings 5
– Read Leveling via MPR

Interface and Power Supply
– SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V)
– SSTL_1353 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)

Options

Speed Grade (CL-TRCD-TRP) 1
– 2133 Mbps / 14-14-14
– 1866 Mbps / 13-13-13
– 1600 Mbps / 11-11-11

Temperature Range (Tc) 3
– Commercial Grade = 0℃~95℃
– Quasi Industrial Grade (-T) = -40℃~95℃
– Industrial Grade (-I) = -40℃~95℃

Programmable Functions

CAS Latency (6/7/8/9/10/11/13/14)
CAS Write Latency (5/6/7/8/9/10)
Additive Latency (0/CL-1/CL-2)
Write Recovery Time (5/6/7/8/10/12/14/16)
Burst Type (Sequential/Interleaved)
Burst Length (BL8/BC4/BC4 or 8 on the fly)
Self RefreshTemperature Range(Normal/Extended)
Output Driver Impedance (34/40)
On-Die Termination of Rtt_Nom(20/30/40/60/120)
On-Die Termination of Rtt_WR(60/120)
Precharge Power Down (slow/fast)

The 2Gb Double-Data-Rate-3 (DDR3(L)) is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAMs.

The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 banks or 16Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications.

The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion.

These devices operate with a single 1.5V ± 0.075V or 1.35V -0.067V/+0.1V power supply and are available in BGA packages.

Descriptions of Nanya NT5CC128M16JR-EK provided by its distributors.

DRAM Chip DDR3L SDRAM 2Gbit 128Mx16 1.35V 96-Pin TFBGA.

Commercial and Industrial DDR3(L) 2Gb SDRAM.

DDR DRAM, 128MX16, CMOS, PBGA96.