In Stock NT5TU32M16FG-AC DDR2 512Mb SDRAM

Basis DDR2 Compliant
– Double-data rate on DQs, DQS, DM bus
– 4n Prefetch Architecture

Throughput of valid Commands
– Posted CAS and Additive Latency (AL)

Signal Integrity
– Configurable DS for system compatibility
– Configurable On-Die Termination
Data Integrity
– Auto Refresh and Self Refresh Modes

Power Saving Modes
– Power Down Mode
– Partial Array Self Refresh (PASR)

SSTL_18 compliance and Power Supply
– VDD/VDDQ = 1.70 to 1.90V

Options

Speed Grade ( DataRate/CL-tRCD-tRP) 1
– 1066 Mbps / 7-7-7
– 800 Mbps / 5-5-5

Temperature Range (Tc) 2
– Commercial Grade = 0℃~95℃
– Quasi Industrial Grade (-T) = -40℃~95℃
– Industrial Grade (-I) = -40℃~95℃

Programmable functions

Output Drive Impedance (Full, Reduced)
Burst Length (4, 8)
Burst Type (Sequential, Interleaved)
Rtt (50, 75, 150)
CAS Latency (5, 6, 7)
Additive Latency (0, 1, 2, 3, 4, 5, 6)
WR (2, 3, 4, 5, 6, 7, 8)
PASR (full, 3/4, 1/2, 1/4

The 512Mb DDR2 SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.

Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for the burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Activate command, which is followed by a Read or Write command. The address bits registered coincident with the activate command are used to select the bank and row to be accesses (BA0-BA1 select the bank, A0-A13 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the Auto-Precharge command is to be issued.

Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command description and device operation.

Organization: 32 Mb x 16
Part Number : NT5TU32M16FG-AC
Package: 84-Ball
Data Rate(Mbps): 800
CL-TRCD-TR: 5-5-5