RS128M16V8DB-107AT DDR3 2Gb 1866Mbps FBGA96

VDD = VDDQ = +1.5V ±0.075V
1.5V center-terminated push / pull I /O
Differen tial bidirectional data strobe
8n -bit prefetch architecture
Differen tial clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
Programmable CAS (READ) latency (CL)
Posted CAS Addictive latency (AL)
Programmable CAS (WRITE) latency (CWL) based on tCK
Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
TC of 0°C to 95°C
– 64ms, 8,192 cycle refresh at 0°C to 85°C
– 32ms, 8,192 cycle refresh at 85°C to 95°C
Self refresh tem perature (SRT)
Write leveling
Multipurpose register
Output driver calibration

Options
Rayson Memory

Configuration
– 512 Meg x 4
– 256 Meg x 8
– 128 Meg x 16

Product Code
– DDR3

Voltage/Refresh
– 1.5V/8k refresh
FBGA package (Pb-free) – x4, x8
– 78-ball (8mm x 10.5mm)
– 78-ball (9mm x 11.5mm)
– 82-ball (12.5mm x 15.5mm)
FBGA package (Pb-free) – x16
– 96-ball (9mm x 14mm)
– 96-ball (8mm x 14mm)
Timing – cycle time
– 0.093ns @ CL = 13 (DDR3-2133)
– 1.07ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)