W9751G6KB-25 8M 4 BANKS 16BIT DDR2 SDRAM

1. GENERAL DESCRIPTION

The W9751G6KB is a 512M bits DDR2 SDRAM, organized as 8,388,608 words  4 banks  16 bits.This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for various applications. W9751G6KB is sorted into the following speed grades: -18, -25, 25I, 25A, 25K and -3.The -18 is compliant to the DDR2-1066 (7-7-7) specification. The -25, 25I, 25A and 25K grade parts are compliant to the DDR2-800 (5-5-5) or DDR2-800 (6-6-6) specification (the 25I industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C). The -3 is compliant to the DDR2-667 (5-5-5) specification.

The automotive grade parts temperature, if offered, has two simultaneous requirements: ambient temperature (TA) surrounding the device cannot be less than -40°C or greater than +95°C (for 25A),+105°C (for 25K), and the case temperature (TCASE) cannot be less than -40°C or greater than +95°C(for 25A), +105°C (for 25K). JEDEC specifications require the refresh rate to double when TCASEexceeds +85°C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance and the input/output impedance must be derated when TCASE is < 0°C or > +85°C.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CLK rising and

CLK falling). All I/Os are synchronized with a single ended DQS or differential DQS- DQS

pair in a source synchronous fashion.

2. FEATURES

 Power Supply: VDD, VDDQ = 1.8 V  0.1V

 Double Data Rate architecture: two data transfers per clock cycle

 CAS Latency: 3, 4, 5, 6 and 7

 Burst Length: 4 and 8

 Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data

 Edge-aligned with Read data and center-aligned with Write data

 DLL aligns DQ and DQS transitions with clock

 Differential clock inputs (CLK and CLK)

 Data masks (DM) for write data

 Commands entered on each positive CLK edge, data and data mask are referenced to both edges of DQS

 Posted CAS programmable additive latency supported to make command and data bus efficiency

 Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)

 Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality

 Auto-precharge operation for read and write bursts

 Auto Refresh and Self Refresh modes

 Precharged Power Down and Active Power Down

 Write Data Mask

 Write Latency = Read Latency - 1 (WL = RL - 1)

 Interface: SSTL_18

 Packaged in WBGA 84 Ball (8X12.5 mm2), using Lead free materials with RoHS compliant