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  •  SN74HC125DR

    TI SN74HC125DR SOIC-14 15mil driver

    Description  This device contains four independent buffers with  3-state outputs. Each gate performs the Boolean  function Y = A in positive logic.

    Hot Tags : TI SN74HC125DR TI driver

  • TLC549CDR

    TI SOP8 TLC549CDR Communication IC

    8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROLThe TLC548 and TLC549 are CMOS analog-to-digital converter (ADC) integrated circuits built around an 8-bitswitched-capacitor  successive-approximation  ADC.  These  devices  are  designed  for  serial  interface  with  amicroprocessor or peripheral through a 3-state data output and an analog input. The TLC548 and TLC549 useonly  the  input/output  clock  (I/O  CLOCK)  input  along  with  the  chip  select  (CS)  input  for  data  control.  Themaximum I/O CLOCK input frequency of the TLC548 is 2.048 MHz, and the I/O CLOCK input frequency of theTLC549 is specified up to 1.1 MHz.

    Hot Tags : TI TLC549CDR Communication IC

  • TL431BIDBZR

    TI SOT-23 TL431BIDBZR Voltage reference chip

    The TL431 and TL432 are three-terminal adjustable shunt regulators, with specified thermal stability over  applicable automotive, commercial, and military temperature ranges. 

    Hot Tags : TI chip TI TL431BIDBZR Voltage reference chip

  • TI TPS61040DBVR 

    TI TPS61040DBVR DC-DC IC SOT-23-5

    The TPS6104x is a high-frequency boost converter  dedicated for small to medium LCD bias supply and  white LED backlight supplies. The device is ideal to  generate output voltages up to 28 V from a dual-cell  NiMH/NiCd or a single-cell Li-Ion battery. The part  can also be used to generate standard 3.3-V or 5-V  to 12-V power conversions.  

    Hot Tags : TI TPS61040DBVR   DC-DC IC

  •  TLC5941RHBR

    TI VQFN-32_EP TLC5941RHBR LED driver

    The TLC5941 is a 16-channel, constant-current sink,  LED driver. Each channel has an individually  adjustable 4096-step grayscale PWM brightness variations between LED channels and other LED  Controlled In-Rush Current  drivers. Both grayscale control and dot correction are accessible via a serial interface. A single external  resistor sets the maximum current value of all 16   channels.

    Hot Tags : TI TLC5941RHBR LED driver

  • TCA9534APWR

    TI TSSOP-16 TCA9534APWR Low power input output (I/O) expander

    TCA9534A is a 16-pin device that provides 8-bit general-purpose parallel input and output (I/O) expansion for the two-wire bidirectional I 2C bus (or SMBus) protocol. The device can operate in a supply voltage range of 1.65V to 5.5V, allowing the use of various devices. The device supports 100kHz (standard mode) and 400kHz (fast mode) clock frequencies. When switches, sensors, buttons, LEDs, fans, and other similar devices require additional I/O, I/O expanders (such as TCA9534A) can provide a simple solution.

    Hot Tags :  Low power input output (I/O) expander TI TCA9534APWR 

  • LM321LVIDBVR

    TI Operational Amplifier LM321LVIDBVR

    The LM3xxLV family includes the single LM321LV,  dual LM358LV, and quad LM324LV operational  amplifiers, or op amps. The devices operate from a  low voltage of 2.7 V to 5.5 V.  

    Hot Tags : Operational Amplifier TI LM321LVIDBVR

  • MT41K256M16LY

    Micron MT41K256M16LY DDR3L SDRAM

    Description  DDR3L SDRAM (1.35V) is a low voltage version of the  DDR3 SDRAM (1.5V).

    Hot Tags : DDR3L SDRAM SDRAM MT41K256M16LY

  •  M12L64164A-5TG2Y

    ESMT DRAM MEMORY M12L64164A-5TG2Y

    1M x 16 Bit x 4 Banks   Synchronous DRAMGENERAL DESCRIPTION   The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by  16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on  every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same  device to be useful for a variety of high bandwidth, high performance memory system applications.

    Hot Tags : DRAM MEMORY ESMT M12L64164A-7TG

  •  M15T4G16256A-DEBG2L

    ESMT DDR3 SDRAM M15T4G16256A-DEBG2L

    32M x 16 Bit x 8 Banks  DDR3(L) SDRAMDescription  The 4Gb Double-Data-Rate-3 (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation. It is internally  configured as an eight-bank DRAM.  The 4Gb chip is organized as 32Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed  double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications.  The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are  synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK  rising and  CK  falling). All I/Os are synchronized with a differential DQS pair in a source synchronous fashion.  These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages.

    Hot Tags : DDR3 SDRAM M15T4G16256A-DEBG2L ESMT

  • M12L2561616A-6TG2A

    ESMT DRAM FLASH M12L2561616A-6TG2A

    4M x 16 Bit x 4 Banks  Synchronous DRAMGENERAL DESCRIPTION   The M12L2561616A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits.  Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.  Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a  variety of high bandwidth, high performance memory system applications.

    Hot Tags : DRAM DRAM FLASH M12L2561616A-6TG2A

  • M15T2G16128A-DEBG2LS

    ESMT DDR3 SDRAM M15T2G16128A-DEBG2LS

    16M x 16 Bit x 8 Banks  DDR3(L) SDRAMDescription  The 2Gb Double-Data-Rate-3(L) (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation. It is  internally configured as an eight bank DRAMs.  The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed  double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications.  The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are  synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK  rising and  CK  falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous  fashion.  These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages.

    Hot Tags : M15T2G16128A-DEBG2LS

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