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  • Winbond W9751G6KB-25

    W9751G6KB-25 8M 4 BANKS 16BIT DDR2 SDRAM

    The W9751G6KB is a 512M bits DDR2 SDRAM, organized as 8,388,608 words  4 banks  16 bits.This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for various applications. W9751G6KB is sorted into the following speed grades: -18, -25, 25I, 25A, 25K and -3.The -18 is compliant to the DDR2-1066 (7-7-7) specification. The -25, 25I, 25A and 25K grade parts are compliant to the DDR2-800 (5-5-5) or DDR2-800 (6-6-6) specification (the 25I industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C). The -3 is compliant to the DDR2-667 (5-5-5) specification.

    Hot Tags : Serial flash memory Winbond flash memory Winbond flash memory agent Serial nor flash memory DDR2 SDRAM Serial flash memory chip

  • Winbond W9825G6KH-6

    Winbond W9825G6KH-6 4 M  4 BANKS  16 BITS SDRAM

    W9825G6KH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 4M words  4 banks  16 bits.

    Hot Tags : Winbond W9825G6KH-6 SDRAM Flash of memory

  • Winbond W9825G6KH-6I

    Winbond W9825G6KH-6I 4 M  4 BANKS  16 BITS SDRAM

    GENERAL DESCRIPTIONW9825G6KH is a high-speed synchronous dynamic random access memory (SDRAM), organized as  4M words  4 banks  16 bits. W9825G6KH delivers a data bandwidth of up to 200M words per  second. To fully comply with the personal computer industrial standard, W9825G6KH is sorted into the  following speed grades: -5, -5I, -6, -6I, -6J, -6L, -75, 75J and 75L.The -5/-5I grade parts are compliant to the 200MHz/CL3 specification (the -5I industrial grade which is  guaranteed to support -40°C ≤ TA ≤ 85°C).The -6/-6I/-6J/-6L grade parts are compliant to the 166MHz/CL3 specification (the -6I industrial grade  which is guaranteed to support -40°C ≤ TA ≤ 85°C, the -6J industrial plus grade which is guaranteed to  support -40°C ≤ TA ≤ 105°C).The -75/75J/75L grade parts are compliant to the 133MHz/CL3 specification (the 75J industrial plus  grade which is guaranteed to support -40°C ≤ TA ≤ 105°C).The -6L and 75L grade parts support self refresh current IDD6 max. 1.5 mA.  Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be  accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE  command. Column addresses are automatically generated by the SDRAM internal counter in burst  operation. Random column read is also possible by providing its address at each clock cycle. The  multiple bank nature enables interleaving among internal banks to hide the precharging time.By having a programmable Mode Register, the system can change burst length, latency cycle,  interleave or sequential burst to maximize its performance. W9825G6KH is ideal for main memory in  high performance applications.2. FEATURES   3.3V ± 0.3V Power Supply   Up to 200 MHz Clock Frequency   4,194,304 Words  4 Banks  16 Bits Organization   Self Refresh Mode: Standard and Low Power   CAS Latency: 2 and 3   Burst Length: 1, 2, 4, 8 and Full Page   Burst Read, Single Writes Mode   Byte Data Controlled by LDQM, UDQM   Power Down Mode   Auto-precharge and Controlled Precharge   8K Refresh Cycles/64 mS, @ -40°C ≤ TA ≤ 85°C   8K Refresh Cycles/16 mS, @ 85°C < TA ≤ 105°C   Interface: LVTTL   Packaged in TSOP II 54-pin, 400 mil - 0.80, using Lead free materials with RoHS compliant

    Hot Tags : memory SDRAM Spi serial flash memory Winbond W9825G6KH-6I Winbond agent

  • EMST M12L64164A-7TG2C

    EMST TOSP-54 M12L64164A-7TG2C SDRAM MEMORY

    1M x 16 Bit x 4 Banks   Synchronous DRAMThe M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits.  Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock  cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be  useful for a variety of high bandwidth, high performance memory system applications.

    Hot Tags : EMST M12L64164A-7TG2C MEMORY SDRAM MEMORY

  • M12L2561616A-6TG2T

    ESMT SDRAM MEMORY M12L2561616A-6TG2T TOSP-54

    4M x 16 Bit x 4 Banks  Synchronous DRAMGENERAL DESCRIPTION  The M12L2561616A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits.  Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.  Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a  variety of high bandwidth, high performance memory system applications.

    Hot Tags : ESMT M12L2561616A-6TG2T

  •  M12L64164A-7TG

    ESMT M12L64164A-7TG TOSP-54 SDRAM MEMORY

    1M x 16 Bit x 4 Banks   Synchronous DRAMGENERAL DESCRIPTION    The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits.  Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock  cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be  useful for a variety of high bandwidth, high performance memory system applications.

    Hot Tags : M12L64164A-7TG

  •  M12L64164A-5TG

    ESMT SDRAM MEMORY M12L64164A-5TG TSOP54

    1M x 16 Bit x 4 Banks   Synchronous DRAMGENERAL DESCRIPTION   The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by  16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on  every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same  device to be useful for a variety of high bandwidth, high performance memory system applications.

    Hot Tags : M12L64164A-5TG

  • M12L128168A-6TG

    ESMT SDRAM MEMORY M12L128168A-6TG SDRAM8*16 TSOP54

    2M x 16 Bit x 4 Banks  Synchronous DRAMGENERAL DESCRIPTION   The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.  Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.  Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a  variety of high bandwidth, high performance memory system applications.
  • M13S2561616A-5TG

    ESMT M13S2561616A-5TG DDR1 SDRAM 16*16

    4M x 16 Bit x 4 Banks   Double Data Rate SDRAM

    Hot Tags : M13S2561616A-5TG

  •  M13S5121632A-5TG

    ESMT SDRAM M13S5121632A-5TG DDR1 32*16

    8M x 16 Bit x 4 Banks   Double Data Rate SDRAM

    Hot Tags : M13S5121632A-5TG

  • M15T2G16128A-DEBG2LS

    ESMT DDR3 SDRAM M15T2G16128A-DEBG2LS

    16M x 16 Bit x 8 Banks  DDR3(L) SDRAMDescription  The 2Gb Double-Data-Rate-3(L) (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation. It is  internally configured as an eight bank DRAMs.  The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed  double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications.  The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are  synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK  rising and  CK  falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous  fashion.  These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages.

    Hot Tags : DDR3 SDRAM M15T2G16128A-DEBG2LS

  •  M15T4G16256A-DEBG2L

    ESMT DDR3 SDRAM M15T4G16256A-DEBG2L

    32M x 16 Bit x 8 Banks  DDR3(L) SDRAMDescription  The 4Gb Double-Data-Rate-3 (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation. It is internally  configured as an eight-bank DRAM.  The 4Gb chip is organized as 32Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed  double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications.  The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are  synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK  rising and  CK  falling). All I/Os are synchronized with a differential DQS pair in a source synchronous fashion.  These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages.

    Hot Tags : M15T4G16256A-DEBG2L

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