Nanya NT5CC256M16EP-EK DDR3 4Gb SDRAM

Descriptions

The 4Gb Double-Data-Rate-3 (DDR3(L)) DRAM is a high-speed CMOS SDRAM containing 4,294,967,296 bits. It is internally configured as an octal-bank DRAM. 

The 4Gb chip is organized as 64Mbit x 8 I/O x 8 banks and 32Mbit x16 I/O x 8 banks. These synchronous devices achieve high speed double-data-rate transfer rates of up to 2133 Mb/sec/pin for general applications.

The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and  falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. 

These devices operate with a single 1.5V ± 0.075V or 1.35V -0.067V/+0.1V power supply and are available in BGA packages.

Features

 Basis DDR3 Compliant

- 8n Prefetch Architecture 

- Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM

 Data Integrity

- Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes  Power Saving Mode

- Power Down Mode

 Signal Integrity

- Configurable DS for system compatibility

- Configurable On-Die Termination

- ZQ Calibration for DS/ODT impedance accuracy via 

external ZQ pad (240 ohm ± 1%) 

 Signal Synchronization 

- Write Leveling via MR settings 5 - Read Leveling via MPR

 Interface and Power Supply

- SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V) - SSTL_1352

for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)