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  • MXIC FLASH MEMORY MX25L12835EMI-10G

    MXIC FLASH MEMORY MX25L12835EMI-10G SOP-16

    HIGH PERFORMANCE  SERIAL FLASH SPECIFICATION128M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY

    Hot Tags : MX25L12835EMI-10G MXIC FLASH MEMORY FLASH MEMORY SERIAL FLASH

  •  MX25L6406EM2I-12G

    MXIC FLASH MEMORY MX25L6406EM2I-12G SOIC-8_208mil

    GENERAL DESCRIPTION  The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.  The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access  to the device is enabled by CS# input.  When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output.  The device provides sequential read operation on whole chip.  After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or  word basis for erase command is executes on sector, or block, or whole chip basis.  To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read  command can be issued to detect completion status of a program or erase operation via WIP bit.  Advanced security features enhance the protection and security functions, please see security features section for  more details.  When the device is not in operation and CS# is high, it is put in standby mode.  The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after typical  100,000 program and erase cycles.

    Hot Tags : MEMORY MX25L6406EM2I-12G FLASH

  • MX25L3206EM2I-12G

    MXIC FLASH MEMORY MX25L3206EM2I-12G SOP-8

    32M-BIT [x 1 / x 2] CMOS SERIAL FLASHGENERAL DESCRIPTION  The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.  The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access  to the device is enabled by CS# input.  When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output.  The device provides sequential read operation on whole chip.  After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or  word basis for erase command is executes on sector, or block, or whole chip basis.  To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read  command can be issued to detect completion status of a program or erase operation via WIP bit.  Advanced security features enhance the protection and security functions, please see security features section for  more details.  When the device is not in operation and CS# is high, it is put in standby mode.  The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after typical  100,000 program and erase cycles.

    Hot Tags : MXIC

  • MX25L1606EM2I-12G

    MXIC FLASH MEMORY MX25L1606EM2I-12G SOIC-8_208mil

    3V, 16M-BIT [x 1/x 2]  CMOS SERIAL FLASH MEMORYKey Features  • Hold Feature  • Low Power Consumption  • Auto Erase and Auto Program Algorithms  • Additional 512 bit secured OTP for unique identifier

    Hot Tags : MX25L1606EM2I-12G

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