GENERAL DESCRIPTION
The GD25Q64C (64M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of 480Mbits/s.
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GDFEATURES
◆ 64M-bit Serial Flash
◆ Fast Program/Erase Speed
-8192K-byte
-Page Program time: 0.6ms typical
-256 bytes per programmable page
-Sector Erase time: 50ms typical
-Block Erase time: 0.15/0.20 typical
◆ Standard, Dual, Quad SPI
-Chip Erase time: 25s typical
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#
◆ Flexible Architecture
-Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
-Uniform Sector of 4K-byte
-Uniform Block of 32/64K-byte
◆ High Speed Clock Frequency
-120MHz for fast read with 30PF load
◆ Low Power Consumption
-Dual I/O Data transfer up to 240Mbits/s
-1μA typical deep power down current
-Quad I/O Data transfer up to 480Mbits/s
-1μA typical standby current
-Continuous Read With 8/16/32/64-byte Wrap
◆ Advanced Security Features(1)
◆ Software/Hardware Write Protection
-128-Bit Unique ID for each device
-Write protect all/portion of memory via software
-3*1024-Byte Security Registers With OTP Locks
-Enable/Disable protection with WP# Pin
-Discoverable parameters (SFDP) register
-Top/Bottom Block protection
◆ Single Power Supply Voltage
◆ Minimum 100,000 Program/Erase Cycles
-Full voltage range:2.7~3.6V
◆ Allows XIP(execute in place)operation(1)
◆ Package Information
-SOP8 (208mil)
◆ Data retention
-DIP8 (300mil)
-20-year data retention typical
-WSON8 (6*5mm)
-WSON8 (8*6mm)
-TFBGA-24(6*4 ball array)
-SOP16 (300mil)
-USON8 (4*4mm)
GENERAL DESCRIPTION The GD25Q16C(16M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of 480Mbits/s.
GENERAL DESCRIPTION The GD25Q32C (32M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#). The Dual I/O data is transferred with speed of 240Mbits/s and the Quad I/O & Quad output data is transferred with speed of 480Mbits/s.
GENERAL DESCRIPTION The GD25Q128C(128M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#) and I/O3 (HOLD#/ RESET#). The Dual I/O data is transferred with speed of 208Mbits/s and the Quad I/O & Quad Output data is transferred with speed of 320Mbits/s.
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TL431LI/TL432LI is a pin-to-pin replacement of TL431/TL432. TL43xLI provides better stability, lower temperature drift (VI(dev)) and lower reference current (Iref), thereby improving system accuracy.TL431 and TL432 devices are three-terminal adjustable shunt regulators, which can meet the specified thermal stability in the applicable automotive, commercial and military temperature ranges. The output voltage can be set to any value between Vref (approximately 2.5V) and 36V through two external resistors.
NuMicro® NUC123 series features a wide voltage operating range of 2.5V to 5.5V, operating temperature:-40 ℃ to 105 ℃, built-in 22.1184 MHz high-precision crystal (1% accuracy). There are rich peripherals such as USB2.0 FS, timer, watchdog timer, UART, SPI, I²C, I²S, PWM, ADC, etc. Provide a variety of packaging QFN33, LQFP48, LQFP64.
For Industrial & Industrial Plus Grade The W25Q128JV supports Dual SPI operation when using instructions such as “Fast Read Dual Output (3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speedcritical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become bidirectional I/O pins: IO0 and IO1.G.
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IPv6 network supported