product
  •  M12L64164A-5TG2Y

    ESMT DRAM MEMORY M12L64164A-5TG2Y

    1M x 16 Bit x 4 Banks   Synchronous DRAMGENERAL DESCRIPTION   The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by  16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on  every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same  device to be useful for a variety of high bandwidth, high performance memory system applications.

    Hot Tags : DRAM MEMORY ESMT M12L64164A-5TG2Y

  •  M15T4G16256A-DEBG2L

    ESMT DDR3 SDRAM M15T4G16256A-DEBG2L

    32M x 16 Bit x 8 Banks  DDR3(L) SDRAMDescription  The 4Gb Double-Data-Rate-3 (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation. It is internally  configured as an eight-bank DRAM.  The 4Gb chip is organized as 32Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed  double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications.  The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are  synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK  rising and  CK  falling). All I/Os are synchronized with a differential DQS pair in a source synchronous fashion.  These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages.

    Hot Tags : DDR3 SDRAM M15T4G16256A-DEBG2L

  • M12L2561616A-6TG2A

    ESMT DRAM FLASH M12L2561616A-6TG2A

    4M x 16 Bit x 4 Banks  Synchronous DRAMGENERAL DESCRIPTION   The M12L2561616A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits.  Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.  Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a  variety of high bandwidth, high performance memory system applications.

    Hot Tags : DRAM DRAM FLASH M12L2561616A-6TG2A

  • M15T2G16128A-DEBG2LS

    ESMT DDR3 SDRAM M15T2G16128A-DEBG2LS

    16M x 16 Bit x 8 Banks  DDR3(L) SDRAMDescription  The 2Gb Double-Data-Rate-3(L) (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation. It is  internally configured as an eight bank DRAMs.  The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed  double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications.  The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are  synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK  rising and  CK  falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous  fashion.  These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages.

    Hot Tags : SDRAM M15T2G16128A-DEBG2LS

  • F50L2G41XA-104YG2B

    ESMT ​SPI-NAND Flash Memory F50L2G41XA-104YG2B

    3.3V 2 Gbit  SPI-NAND Flash MemoryGENERAL DESCRIPTION  Serial peripheral interface (SPI) NAND is an SLC NAND Flash memory device that provides a cost-effective nonvolatile memory  storage solution where pin count must be kept to a minimum. It is also an alternative solution to SPI NOR, offering superior write  performance and cost per bit over SPI NOR. The hardware interface creates a low pincount device with a standard pinout that remains  the same from one density to another and supports future upgrades to higher densities without board redesign.

    Hot Tags : ​SPI-NAND Flash F50L2G41XA-104YG2B Memory

  •  M13S5121632A-5TG

    ESMT SDRAM M13S5121632A-5TG DDR1 32*16

    8M x 16 Bit x 4 Banks   Double Data Rate SDRAM

    Hot Tags : M13S5121632A-5TG

  • M13S2561616A-5TG

    ESMT M13S2561616A-5TG DDR1 SDRAM 16*16

    4M x 16 Bit x 4 Banks   Double Data Rate SDRAM

    Hot Tags : M13S2561616A-5TG

  • M12L128168A-6TG

    ESMT SDRAM MEMORY M12L128168A-6TG SDRAM8*16 TSOP54

    2M x 16 Bit x 4 Banks  Synchronous DRAMGENERAL DESCRIPTION   The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.  Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.  Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a  variety of high bandwidth, high performance memory system applications.

    Hot Tags : SDRAM MEMORY

  •  M12L64164A-5TG

    ESMT SDRAM MEMORY M12L64164A-5TG TSOP54

    1M x 16 Bit x 4 Banks   Synchronous DRAMGENERAL DESCRIPTION   The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by  16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on  every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same  device to be useful for a variety of high bandwidth, high performance memory system applications.

    Hot Tags : M12L64164A-5TG

  •  M12L64164A-7TG

    ESMT M12L64164A-7TG TOSP-54 SDRAM MEMORY

    1M x 16 Bit x 4 Banks   Synchronous DRAMGENERAL DESCRIPTION    The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits.  Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock  cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be  useful for a variety of high bandwidth, high performance memory system applications.

    Hot Tags : M12L64164A-7TG

  • M12L2561616A-6TG2T

    ESMT SDRAM MEMORY M12L2561616A-6TG2T TOSP-54

    4M x 16 Bit x 4 Banks  Synchronous DRAMGENERAL DESCRIPTION  The M12L2561616A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits.  Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.  Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a  variety of high bandwidth, high performance memory system applications.

    Hot Tags : M12L2561616A-6TG2T

  • EMST M12L64164A-7TG2C

    EMST TOSP-54 M12L64164A-7TG2C SDRAM MEMORY

    1M x 16 Bit x 4 Banks   Synchronous DRAMThe M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits.  Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock  cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be  useful for a variety of high bandwidth, high performance memory system applications.

    Hot Tags : EMST M12L64164A-7TG2C MEMORY

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