8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROLDescriptionThe TLC548 and TLC549 are CMOS analog-to-digital converter (ADC) integrated circuits built around an 8-bitswitched-capacitor  successive-approximation  ADC.  These  devices  are  designed  for  serial  interface  with  amicroprocessor or peripheral through a 3-state data output and an analog input. The TLC548 and TLC549 useonly  the  input/output  clock  (I/O  CLOCK)  input  along  with  the  chip  select  (CS)  input  for  data  control.  Themaximum I/O CLOCK input frequency of the TLC548 is 2.048 MHz, and the I/O CLOCK input frequency of theTLC549 is specified up to 1.1 MHz.Operation of the TLC548 and the TLC549 is very similar to that of the more complex TLC540 and TLC541devices; however, the TLC548 and TLC549 provide an on-chip system clock that operates typically at 4 MHzand requires no external components. The on-chip system clock allows internal device operation to proceedindependently of serial input/output data timing and permits manipulation of the TLC548 and TLC549 as desiredfor a wide range of software and hardware requirements. The I/O CLOCK together with the internal system clockallow high-speed data transfer and conversion rates of 45 500 conversions per second for the TLC548, and40 000 conversions per second for the TLC549.Additional TLC548 and TLC549 features include versatile control logic, an on-chip sample-and-hold circuit thatcan  operate  automatically  or  under  microprocessor  control,  and  a  high-speed  converter  with  differentialhigh-impedance reference voltage inputs that ease ratiometric conversion, scaling, and circuit isolation fromlogic and supply noises. Design of the totally switched-capacitor successive-approximation converter circuitallows conversion with a maximum total error of ±0.5 least significant bit (LSB) in less than 17 μs.The TLC548C and TLC549C are characterized for operation from 0°C to 70°C. The TLC548I and TLC549I arecharacterized for operation from – 40°C to 85°C

description/ordering informationThe TL431 and TL432 are three-terminal adjustable shunt regulators, with specified thermal stability over  applicable automotive, commercial, and military temperature ranges. The output voltage can be set to any value  between Vref (approximately 2.5 V) and 36 V, with two external resistors (see Figure 17). These devices have  a typical output impedance of 0.2 Ω. Active output circuitry provides a very sharp turn-on characteristic, making  these devices excellent replacements for Zener diodes in many applications, such as onboard regulation,  adjustable power supplies, and switching power supplies. The TL432 has exactly the same functionality and  electrical specifications as the TL431, but has different pinouts for the DBV and DBZ packages.  Both the TL431 and TL432 devices are offered in three grades, with initial tolerances (at 25°C) of 0.5%, 1%,  and 2%, for the B, A, and standard grade, respectively. In addition, low output drift vs temperature ensures good  stability over the entire temperature range.  The TL43xxC devices are characterized for operation from 0°C to 70°C, the TL43xxI devices are characterized  for operation from −40°C to 85°C, and the TL43xxQ devices are characterized for operation from −40°C to  125°C.

Description  The TPS6104x is a high-frequency boost converter  dedicated for small to medium LCD bias supply and  white LED backlight supplies. The device is ideal to  generate output voltages up to 28 V from a dual-cell  NiMH/NiCd or a single-cell Li-Ion battery. The part  can also be used to generate standard 3.3-V or 5-V  to 12-V power conversions.  The TPS6104x operates with a switching frequency  up to 1 MHz. This frequency allows the use of small  external components using ceramic as well as  tantalum output capacitors. Together with the thin  WSON package, the TPS6104x gives a very small  overall solution size. The TPS61040 device has an  internal 400-mA switch current limit, while the  TPS61041 device has a 250-mA switch current limit,  offering lower output voltage ripple and allows the  use of a smaller form factor inductor for lower power  applications. The low quiescent current (typically 28  μA) together with an optimized control scheme,  allows device operation at very high efficiencies over  the entire load current range.

DESCRIPTIONThe TLC5941 is a 16-channel, constant-current sink,  LED driver. Each channel has an individually  adjustable 4096-step grayscale PWM brightness variations between LED channels and other LED  Controlled In-Rush Current  drivers. Both grayscale control and dot correction are accessible via a serial interface. A single external  resistor sets the maximum current value of all 16   channels.The TLC5941 features two error information circuits.The LED open detection (LOD) indicates a broken or disconnected LED at an output terminal. The thermal  error flag (TEF) indicates an overtemperature  condition.

DescriptionTCA9534A is a 16-pin device that provides 8-bit general-purpose parallel input and output (I/O) expansion for the two-wire bidirectional I 2C bus (or SMBus) protocol. The device can operate in a supply voltage range of 1.65V to 5.5V, allowing the use of various devices. The device supports 100kHz (standard mode) and 400kHz (fast mode) clock frequencies. When switches, sensors, buttons, LEDs, fans, and other similar devices require additional I/O, I/O expanders (such as TCA9534A) can provide a simple solution.The functions of TCA9534A include generating an interrupt on the INT pin. In this way, the master device knows when the input port status has changed. The hardware selectable address pins A0, A1, and A2 allow up to 8 TCA9534A devices to be on the same I 2C bus. The device can also be powered by power cycling to generate a power-on reset, thereby resetting to the default state. Device

Description  The LM3xxLV family includes the single LM321LV,  dual LM358LV, and quad LM324LV operational  amplifiers, or op amps. The devices operate from a  low voltage of 2.7 V to 5.5 V.  These op amps supply an alternative to the LM321,  LM358, and LM324 in low-voltage applications that  are sensitive to cost. Some applications are large  appliances, smoke detectors, and personal  electronics. The LM3xxLV devices supply better  performance than the LM3xx devices at low voltage,  and have lower power consumption. The op amps  are stable at unity gain, and do not have reverse  phase in overdrive conditions. The design for ESD  gives the LM3xxLV family an HBM specification for a  minimum of 2 kV.  The LM3xxLV family is available in packages that  have industry standards. The packages include SOT23, SOIC, VSSOP, and TSSOP packages

Description  DDR3L SDRAM (1.35V) is a low voltage version of the  DDR3 SDRAM (1.5V).

1M x 16 Bit x 4 Banks   Synchronous DRAMGENERAL DESCRIPTION   The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by  16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on  every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same  device to be useful for a variety of high bandwidth, high performance memory system applications.

32M x 16 Bit x 8 Banks  DDR3(L) SDRAMDescription  The 4Gb Double-Data-Rate-3 (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation. It is internally  configured as an eight-bank DRAM.  The 4Gb chip is organized as 32Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed  double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications.  The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are  synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK  rising and  CK  falling). All I/Os are synchronized with a differential DQS pair in a source synchronous fashion.  These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages.

4M x 16 Bit x 4 Banks  Synchronous DRAMGENERAL DESCRIPTION   The M12L2561616A is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits.  Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.  Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a  variety of high bandwidth, high performance memory system applications.

16M x 16 Bit x 8 Banks  DDR3(L) SDRAMDescription  The 2Gb Double-Data-Rate-3(L) (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation. It is  internally configured as an eight bank DRAMs.  The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed  double-data-rate transfer rates of up to 1866 Mb/sec/pin for general applications.  The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are  synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK  rising and  CK  falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous  fashion.  These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages.

3.3V 2 Gbit  SPI-NAND Flash MemoryGENERAL DESCRIPTION  Serial peripheral interface (SPI) NAND is an SLC NAND Flash memory device that provides a cost-effective nonvolatile memory  storage solution where pin count must be kept to a minimum. It is also an alternative solution to SPI NOR, offering superior write  performance and cost per bit over SPI NOR. The hardware interface creates a low pincount device with a standard pinout that remains  the same from one density to another and supports future upgrades to higher densities without board redesign.